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RAM Mapping 32 X 4 LCD Controller for I/O uC
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General Descriptions The SS1621 is a 128-pattern (32x4), memory mapping, and multi-function LCD driver. The S/W configuration feature of the SS1621 makes it suitable for multiple LCD applications including LCD modules and display subsystems. Only three or four lines are required for the interface between the host controller and the SS1621. The SS1621 contains a power down command to reduce power consumption.
Features
* * * * * * * * * * * * * * * * * * *
Operating voltage: 2.4V~5.2V. Built-in 256kHz RC oscillator. External 32.768kHz crystal or 256kHz frequency source input. Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications. Internal time base frequency sources. Two selectable buzzer frequencies (2kHz/4kHz). Built-in time base generator and WDT. Time base or WDT overflow output. Power down command reduces power Consumption. 8 kinds of time base/WDT clock sources. 32x4 LCD driver. Built-in 32x4 bit display RAM. 3-wire serial interface. Internal LCD driving frequency source. Software configuration feature. Data mode and command mode instructions. R/W address auto increment. Three data accessing modes. VLCD pin for adjusting LCD operating voltage.
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SS1621
Block Diagram
BZ
BZ
Tone Generator
Watchdog Timer & Time Base Generator
IRQ
VLCD COM0
VDD GND
CS
WR
RD
DATA
Control Logic & Timing Generator
LCD Driver & Bias Circuit
COM3 SEG0 SEG31
OSCI OSCO Display Memory
Note: CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface IRQ: Time base or WDT overflow output COM0~COM3, SEG0~SEG31: LCD outputs
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SS1621
Pin Assignment
SS1621B-48SSOP
SS1621D-28SKDIP
SS1621B -48LQFP
SS1621BL -48LQFP
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SS1621
PIN Description
PIN Name I/O Function Chip selection input with pull-high resistor When the CS is logic high, the data and command read from or written to the SS1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the SS1621 are all enabled.
CS
I
RD
I
READ clock input with pull-high resistor Data in the RAM of the SS1621 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data.
WRITE clock input with pull-high resistor Data on the DATA line are latched into the SS1621 on the rising edge of the WR signal. Serial data input/output with pull-high resistor Negative power supply, ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if and on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. LCD power input Positive power supply Time base or WDT overflow flag, NMOS open drain output 2kHz or 4kHz tone frequency output pair LCD common outputs LCD segment outputs
WR DATA GND OSCO OSCI VLCD VDD
IRQ
I I/O -- O I I -- O O O O
BZ, BZ COM0~COM3 SEG0~SEG31
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SS1621
Absolute Maximum Ratings
Supply Voltage.......................-0.3V ~ 5.5V Input Voltage......... VSS - 0.3V ~ VDD + 0.3V
Storage Temperature...............-50C ~ 125C Operating Temperature..............-25C ~ 75C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 IDD2 IDD3 ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 RPH Parameter Operating Voltage Operating Current Operating Current Operating Current Standby Current Input Low Voltage Input High Voltage DATA, BZ, BZ, IRQ DATA, BZ, BZ LCD Common Sink Current LCD Common Source Current LCD Segment Sink Current LCD Segment Source Current Pull-high Resistor VDD -- 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Test Conditions Conditions -- No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator No load/LCD ON External clock source No load Power down mode DATA, WR, CS, RD DATA, WR, CS, RD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5 V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5 V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5 V DATA, WR, CS, RD Min. 2.4 -- -- -- -- -- -- -- -- 0 0 2.4 4.0 0.5 1.3 -0.4 -0.9 80 150 -80 -120 60 120 -40 -70 40 30 Typ. -- 150 300 60 120 100 200 0.1 0.3 -- -- -- -- 1.2 2.6 -0.8 -1.8 150 250 -120 -200 120 200 -70 -100 80 60 Max. 5.2 300 600 120 240 200 400 5 10 0.6 1.0 3.0 5.0 -- -- -- -- -- -- -- -- -- -- -- -- 150 100 Unit V A A A A A A A A V V V V mA mA mA mA A A A A A A A A k k
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SS1621
A.C. Characteristics
Sym. Parameter VDD fSYS1 System Clock fSYS2 System Clock fSYS3 System Clock 3V 5V 3V 5V 3V 5V -- Test Conditions Conditions On-chip RC oscillator Crystal oscillator External clock source On-chip RC oscillator fLCD LCD Clock tCOM LCD Common Period fCLK1 Serial Data Clock (WR Pin) fCLK2 Serial Data Clock (RD Pin) fTONE Tone Frequency tCS Serial Interface Reset Pulse Width (Figure 3) 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V -- -- 100 -- ns -- -- 100 -- ns -- -- 120 -- ns -- -- 120 -- ns 3V 5V 3V 5V Crystal oscillator External clock source n: Number of COM Duty cycle 50% Duty cycle 50% On-chip RC oscillator
CS
Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.34 6.67 1.67 3.34
Typ. 256 256 32.768 32.768 256 256 FSYS1/1024 FSYS2/128 FSYS3/1024 n/fLCD
Max. -- -- -- -- -- -- -- -- -- -- 150 300 75 150
Unit kHz kHz kHz kHz kHz kHz Hz Hz Hz s kHz kHz kHz kHz kHz ns
2.0 or 4.0 250 -- -- -- -- 120
-- -- -- -- -- -- --
Write mode Read mode Write mode Read mode --
tCLK
WR, RD Input Pulse Width (Figure 1)
s s
Rise/Fall Time Serial Data Clock tr, tf Width (Figure 1) tsu Setup Time for DATA to WR, RD Clock Width (Figure 2) Hold Time for DATA to WR, RD Clock Width (Figure 2) Setup Time for CS to WR, RD Clock Width (Figure 3) Hold Time for CS to WR, RD Clock Width (Figure 3)
--
ns
th
tsu1
th1
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SS1621
tf WR, RD Clock 90% 50% 10% tCLK tCLK WR, RD Clock tf VDD GND VALID DATA DB 50% GND tSU th VDD 50% GND VDD
Figure 1
tCS CS 50% GND tsu1 WR, RD Clock 50% FIRST Clock LAST Clock GND th1 VDD VDD
Figure 2
Figure 3
Functional Description
Display memory - RAM
The static display memory (RAM) is organized into 32x4 bits and stores the displayed data. The contents of the RAM are directly mapped to the contents of the LCD
COM3 SEG0 SEG1 SEG2 SEG3 COM2 COM1 COM0 0 1 2 3 Address 6 bits (A5, A4, ..., A0)
the READ, WRITE, and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD pattern:
System oscillator
SEG31 D3 D2 D1 D0
31 Data Addr
Data 4 bits (D3, D2, D1, D0)
RAM mapping
driver. Data in the RAM can be accessed by
OSCI OSCO Crystal Oscillator 32768Hz
The SS1621 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The source of the clock may be from an on-chip RC oscillator (256kHz), a crystal oscillator (32.768kHz), or an external 256kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is, however, available only for the
External Clock Source 256kHz 1/8 On-chip RC Oscillator 256kHz
System Clock
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SS1621
on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT lose its function as well. The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 256kHz clock source operation. At the initial system power on, the SS1621 is at the SYS DIS state.
Time base and Watchdog Timer (WDT)
Where the value of n ranges from 0 to 7 by command options. The 32kHz in the above equation indicates that the source of the system frequency is derived from a crystal oscillator of 32.768kHz, an on-chip oscillator (256kHz), or an external frequency of 256kHz. If an on-chip oscillator (256kHz) or an external 256kHz frequency is chosen as the source of the system frequency, the frequency source is by default prescaled to 32kHz by a 3-stage prescaler. Employing both the time base generator and the WDT related commands, one should be careful since the time base generator and WDT share the same 8-stage counter. For example, invoking the WDT DIS command disables the time base generator whereas executing the WDT EN command not only enables the time base generator but activates the WDT time-out flag output (connect the WDT time-out flag to the IRQ pin). After the TIMER EN command is transferred, the WDT is disconnected from the IRQ pin, and the output of the time base generator is connected to the IRQ pin. The WDT can be cleared by executing the CLR WDT command, and the contents of the base time generator is cleared by executing the CLR WDT or the CLR TIMER command. The CLR WDT or the CLR TIMER command should be executed prior to the WDT EN or the TIMER EN command respectively. Before executing the IRQ EN command the CLR WDT or CLR TIMER command should be executed first. The CLR TIMER command has to be executed before switching from the WDT mode to the time base mode. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued. After the IRQ output is disabled the IRQ pin will remain at the floating state. The IRQ output can be enabled or disabled by executing the IRQ EN or the IRQ DIS command, respectively. The IRQ EN makes the output of the time base
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The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an accurate time base. The watch dog timer (WDT), on the other hand, is composed of and 8-stage time base generator along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT time-out will result in the setting of and internal WDT time-out flag. The outputs of the time base generator and of the WDT time-out flag can be connected to the IRQ output by a command option. There are totally eight frequency sources available for the time base generator and the WDT clock. The frequency is calculated by the following equation.
f WDT = 32kHz 2n
SS1621
Name LCD OFF LCD ON Command Code 10000000010X 10000000011X Function Turn off LCD outputs Turn on LCD outputs c=0:1/2 bias option c=1:1/3 bias option ab=00:2 commons option ab=01:3 commons option ab=10:4 commons option
BIAS & COM 1 0 0 0 0 1 0 a b X c X
generator or of the WDT time-out flag appear on the IRQ pin. The configuration of the time base generator along with the WDT are as shown. In the case of on-chip RC oscillator or crystal oscillator, the power down mode can reduce power consumption since the oscillator can be turned on or off by the corresponding system commands. At the power down mode the time base/WDT loses all its functions. On the other hand, if an external clock is selected as the source of sys tem frequency the SYS DIS command turns out invalid and the power down mode fails to be carried out. That is, after the external clock source is selected, the SS1621 will continue working until system power fails or the external clock source is removed. After the system power on, the IRQ will be disabled.
Tone output
LCD driver
The SS1621 is a 128 (32x4) patterns LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of LCD driver by the S/W configuration. This feature makes the SS1621 suitable for multiply LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is always 256Hz even when it is at a 32.768kHz crystal oscillator frequency, or an external frequency. The LCD corresponding commands are summarized in the table. The bold form of 100, namely 100, indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The LCD OFF command turns the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related commands. Using the LCD related commands; the SS1621 can be compatible with most types of LCD panels.
Command format
A simple tone generator is implemented in the SS1621. The tone generator can output a pair of differential driving signals on the BZ and BZ, which are used to generate a single tone. By executing the TONE4K and TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned on or off by invoking the TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZ, area pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ output will remain at low level.
The SS1621 can be configured by the S/W setting. There are two mode commands to configure the SS1621 resources and to transfer the LCD display data. The configuration mode of the SS1621 is called command mode, and its command mode IC is 100. The command mode consists of system configuration command, a system frequency selection command, a LCD configuration command, a tone frequency selection command, a
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SS1621
timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode Ids and the command mode ID:
Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data Command ID 110 101 101 100
The mode command should be issued before the data or command is transferred. If successive commands have been issued, the command mode ID, namely 100, can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to "1" and the previous operation mode will be reset also. Once the CS pin returns to "0" a new operation mode ID should be issued first.
Interfacing
Only four lines are required to interface with the SS1621. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host
controller and the SS1621. If the CS pin is set to 1, the data and command issued between the host controller and the SS1621 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the SS1621. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DATA line. It is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the SS1621 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the SS1621. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by being connected with the IRQ pin of the SS1621.
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SS1621
Timing Diagrams
READ mode (command code: 1 1 0 )
CS
WR
RD
DATA
1
1
0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 1 (MA1) Data (MA1)
1
1
0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 2 (MA2) Data (MA2)
CS
WR
RD
DATA
1
1
0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 Memory Address (MA) Data (MA) Data (MA+1) Data (MA+2) Data (MA+3)
READ mode (successive address reading) WRITE mode (command code: 1 0 1 ) WRITE mode (successive address writing)
CS
WR
DATA
1
0
1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 Memory Address (MA) Data (MA) Data (MA+1) Data (MA+2) Data (MA+3)
CS
WR
DATA
1
0
1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 1 (MA1) Data (MA1)
1
0
1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 2 (MA2) Data (MA2) Last update: 2008-06-03 04:36
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SS1621
READ-MODIFY-WRITE mode (command code: 1 0 1 )
CS WR
RD DATA
1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 Memory Address 1 (MA1) Data (MA1) Data (MA1) 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 Memory Address 2 (MA2) Data (MA2) Data (MA2)
READ-MODIFY-WRITE mode (successive address accessing)
CS WR RD DATA
1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 Memory Address (MA) Data (MA) Data (MA) Data (MA+1) Data (MA+1) Data (MA+2) Data (MA+2)
Command mode (command code: 1 0 0 )
CS
WR
DATA
1
0
0 C8 C7 C6 C5 C4 C3 C2 C1 C0 Command 1
C8 C7 C6 C5 C4 C3 C2 C1 C0 Command i Command or Data Mode
Command...
Mode (data and command mode)
CS
WR
DATA Command Address & Data or Data Mode RD Command Address & Data or Data Mode Command Address & Data or Data Mode
Note: It is recommended that the host controller should read in the data from the DATA line between the rising edge of the RD line and the falling edge of the next RD line.
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SS1621
Application Circuits
Host controller with a SS1621 display system
CS
* C
VDD RD WR DATA * VLCD
VR
*
SS1621
BZ
R
IRQ OSCI Clock Out External Clock 1 External Clock 2 On-chip OSC OSCO COM0 ~ COM3 SEG0 ~ SEG31
Piezo
BZ
1/2 or 1/3 Bias; 1/2, 1/3 or 1/4 Duty
LCD PANEL
Crystal 32768Hz
Note: The connection of IRQ and RD pin can be selected depending on the requirement of the C. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15k+20% Adjust R (external pull-high resistance) to fit user's time base clock.
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SS1621
Command Summary
Name READ WRITE READ-MODIFY-WRITE SYS DIS SYS EN LEC OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN TONE OFF TONE ON CLR TIMER CLR WDT XTAL 32K RC 256K EXT 256K ID Command Code D/C Function Def.
1 1 0 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D1D2D3 1 0 0 0000-0000-X 1 0 0 0000-0001-X 1 0 0 0000-0010-X 1 0 0 0000-0011-X 1 0 0 0000-0100-X 1 0 0 0000-0101-X 1 0 0 0000-0110-X 1 0 0 0000-0111-X 1 0 0 0000-1000-X 1 0 0 0000-1001-X 1 0 0 0000-11XX-X 1 0 0 0000-111X-X 1 0 0 0001-01XX-X 1 0 0 0001-10XX-X 1 0 0 0001-11XX-X
D Read data from the RAM D Write data to the RAM D READ and WRITE to the RAM C Turn off system oscillator and LCD Yes bias generator Yes
C Turn on system oscillator C Turn off LCD bias generator C Turn on LCD bias generator C Disable time base output C Disable WDT time-out flag output C Enable time base output C Enable WDT time-out flag output C Turn off tone outputs C Turn on tone outputs C Clear the contents of time base generator System clock source, crystal oscillator System clock source, external clock Yes source System clock source, external clock source Yes
C Clear the contents of WDT stage C C C
BLAS 1/2
1 0 0 0010-abX0-X
LCD 1/2 bias option ab=00:2 commons option C ab=01:3 commons option ab=10:4 commons option LCD 1/3 bias option ab=00:2 commons option C ab=01:3 commons option ab=10:4 commons option C Tone frequency, 4kHz C Tone frequency, 2kHz C Disable IRQ output C Enable IRQ output Time base/WDT clock C Output: 1Hz The WDT time-out flag after: 4s C Time base/WDT clock Output: 2Hz p. 14
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BLAS 1/3
1 0 0 0010-abX1-X
TONE 4K TONE 2K
IRQ DIS IRQ EN
1 0 0 010X-XXXX-X 1 0 0 011X-XXXX-X 1 0 0 100X-0XXX-X 1 0 0 100X-1XXX-X 1 0 0 101X-X000-X 1 0 0 101X-X001-X
Yes
F1 F2
SS1621
Name ID Command Code D/C Function The WDT time-out flag after: 2s F4 1 0 0 101X-X010-X Time base/WDT clock C Output: 4Hz The WDT time-out flag after: 1s Time base/WDT clock C Output: 8Hz The WDT time-out flag after: 1/2s Time base/WDT clock C Output: 16Hz The WDT time-out flag after: 1/4s Time base/WDT clock C Output: 32Hz The WDT time-out flag after: 1/8s Time base/WDT clock C Output: 64Hz The WDT time-out flag after: 1/16s Time base/WDT clock C Output: 128Hz Yes The WDT time-out flag after: 1/32s C C Yes Def.
F8
1 0 0 101X-X011-X
F16
1 0 0 101X-X100-X
F32
1 0 0 101X-X101-X
F64
1 0 0 101X-X110-X
F128 TEST NORMAL
1 0 0 101X-X111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X
Note: X: Don't care A5~A0: RAM addresses D3~D0: RAM data D/C: Data/command mode Def.: Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 256kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 256kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the SS1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the SS1621.
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